1. Field of the Invention
The present invention relates generally to the field of digital division. More particularly, the present invention provides for faster and more efficient digital division in integrated circuits.
2. Description of the Related Art
Digital, or binary, division is a process whereby a binary number, referred to as a dividend is divided by a second binary number referred to as a divider. Digital division is increasingly required for many applications such as high quality graphics rendering. Unfortunately, division circuits are usually much larger than multiplier circuits for an equivalent data word length. One conventional method of performing digital division known as restoring and non-restoring division typically involves subtracting the divider from a reference number referred to as a current number. These methods of performing digital division generally require that the divider be added back to the current number after each computation stage. In the restoring method, the decision whether to add back the divider to the current number depends on the result of a subtraction stage. In the non-restoring method, a selection between addition and subtraction is made in the next computation stage following the subtraction stage. In either case, substantial amounts of logic and related logic circuitry are required to implement restoring and non-restoring division. Such additional logic typically can include at least an exclusive-OR (XOR) gate for every bit, which is the equivalent of five (5) NAND gates for every bit.
Hence, conventional techniques for implementing digital division require substantial amounts of logic resources and related logic circuitry. When the integrated circuit is a programmable logic device (PLD), large amounts of valuable programming resources are required to implement digital division, thereby limiting the size or precision of the data words that can be accommodated. Additionally, the serpentine data paths required to connect the related logic circuitry within a particular integrated circuit result in slow performance and can, in some cases, cause the integrated circuit to be non-functional.
In view of the foregoing, it would be advantageous and therefore desirable to provide an efficient method of performing digital division that can be implemented in an integrated circuit using fewer logical resources. By using fewer logical resources, the precision and the speed of the digital division as performed by the integrated circuit are able to be increased. Additionally, the probability of successfully implementing the digital division in an integrated circuit, such as PLD, is commensurably increased.